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LHF16KS1
6.2.5 AC CHARACTERISTICS - WRITE OPERATIONS (1)
V CC =5V±0.5V, 5V±0.25V, T A =-40°C to +85°C
39
V CC =5V±0.25V
LH28F160S5H-
L70 (7)
Versions (5)
V CC =5V±0.5V
LH28F160S5H-
L90 (8)
Sym.
Parameter
Notes
Min.
Max.
Min.
Max.
Unit
t AVAV
Write Cycle Time
70
90
ns
t PHWL
t ELWL
t WLWH
t SHWH
t VPWH
t AVWH
t DVWH
t WHDX
t WHAX
t WHEH
t WHWL
t WHRL
t WHGL
t QVVL
t QVSL
t FVWH
t WHFV
RP# High Recovery to WE# Going
Low
CE# Setup to WE# Going Low
WE# Pulse Width
WP# V IH Setup to WE# Going High
V PP Setup to WE# Going High
Address Setup to WE# Going High
Data Setup to WE# Going High
Data Hold from WE# High
Address Hold from WE# High
CE# Hold from WE# High
WE# Pulse Width High
WE# High to STS Going Low
Write Recovery before Read
V PP Hold from Valid SRD, STS High Z
WP# V IH Hold from Valid SRD, STS
High Z
BYTE# Setup to WE# Going High
BYTE# Hold from WE# High
2
2
2
3
3
2,4
2,4
1
10
40
100
100
40
40
5
5
10
30
0
0
0
50
NOTE 6
90
1
10
40
100
100
40
40
5
5
10
30
0
0
0
50
NOTE 6
90
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Read timing characteristics during block erase, full chip erase, (multi) wrod/byte write and block lock-bit
configuration operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
2. Sampled, not 100% tested.
3. Refer to Table 4 for valid A IN and D IN for block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration.
4. V PP should be held at V PPH1 until determination of block erase, full chip erase, (multi) word/byte write or block
lock-bit configuration success (SR.1/3/4/5=0).
5. See Ordering Information for device speeds (valid operational combinations).
6. BYTE# should be in stable until determination of block erase, full chip erase, (multi) word/byte write, block lock-
bit configuration or STS configuration success (SR.7=1).
7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed
Configuration) for testing characteristics.
8. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 2.0
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